In the course of the increasing integration of widely differing components in an appliance, it appears to be worthwhile to make use of the components which are already present in an appliance, and/or the resources of different components, that is to say more than once. Thus, for example, particularly in the mobile radio sector, it is possible to integrate a peripheral device, such as a Bluetooth module, in a GSM, CDMA cellular telephone, as a host device or host. The peripheral device or module should in this case use the same system clock, typically for example 10-100 MHz, as the main device or the host device.
FIG. 3 shows, schematically, a known arrangement for implementation of data interchange 14 between a first interface 11 of a host 10, and a second interface 13 of a peripheral module or of a peripheral device 12, as a function of a system clock 15. The main device 10 or the host and the peripheral module 12 in this case each interchange data 14 via an interface 11, 13. In order to allow the system costs to be reduced and in order to allow multiple use, both the host 10 and the module 12 are able to process and to cover a certain frequency range of system clocks 15 and their frequencies.
In order to make is possible to ensure this, it is necessary to configure both the host 10 and the peripheral module 12 to the system clock 15. One possible known arrangement is shown in FIG. 2, as an example of the peripheral module 12. The system clock 15 is supplied to the peripheral device 12 and is processed by a PLL (phase locked loop) 17, using a constant clock 18, which in turn is supplied to an interface 13 and/or to a processing device 19, for example a processor, a controller or a memory.
In order now, by way of example, to achieve a cost reduction for the overall system, the system is designed such that only the host 10 knows the precise system clock, and/or the host 10 can vary the clock during operation and must then signal this to the module 12. The module 12 therefore has no separate memory or the like containing any information about the system clock. The interface 13 of the module 12 must be configured to a specific transmission rate, typically, for example, 10 kbaud to 10 Mbaud, in which case this interface transmission rate must be within a specific tolerance band both for the main device 10 and for the peripheral module 12, with this tolerance band being defined, for example, by an interface standard. In this case, the actual transmission rate is dependent on the system clock 15, when the clock for supplying the individual internal components 13, 17, 19 of the peripheral device 12 is derived from the system clock 15 and, in consequence, in proportion to it.
In the known arrangement shown in FIG. 3, the information about the system clock 15 can be signaled to the module 12 in such a way that, in the initialization phase, all of the internal components 13, 17, 19 of the module 12 are supplied with the system clock 15 or with predetermined clock ratios of this clock. This precondition must be ensured by the module 12 both in terms of hardware and software in a predetermined minimum/maximum range of the system clock 15. The transmission rate of the interface 13 is then chosen as a fixed ratio to the system clock 15, thus ensuring that the main device 10 and the peripheral device 12 have the same transmission rate at the interfaces 11, 13, and can thus communicate with one another. The information about the system clock, and likewise about the desired transmission rate for the interfaces 11, 13, is then signaled to the module 12 via this interface 13. The host 10 can then switch the interface transmission rate once the module has been configured to the known system clock 15 and the interface transmission rate has been set.
Complex configuration of the peripheral module to the system clock must therefore be carried out. Furthermore, the known system implementation is based on the principle that the transmission rate of the interface must be set as a fixed ratio to the system clock in the initialization phase, in order that the host and the module provide the same transmission rate at their interfaces.